Design and analysis of SOI and SELBOX junctionless FinFET at sub-15 nm technology node

Abstract

The structural and operational characteristics of a silicon on insulator (SOI) junctionless (JL) FinFET have been compared with the selective buried oxide (SELBOX) JL FinFET for 15 nm gate length and beyond using simulation studies. Simulations have been performed using silvaco TCAD (Atlas 3-D Module). SELBOX JL FinFET device has shown ~10 times improvement in I_ON/I_OFF ratio with respect to the SOI JL FinFET. The SELBOX based device has subthreshold slope (SS) value of 69.08 mV/Dec whereas this is 84.1 mV/Dec for SOI based device. SELBOX JL FinFET has DIBL value of 31.57 mV/V whereas this is 119 mV/V for SOI JL FinFET. The comparison results, discussed, are for the channel length (gate length) of 15 nm. Furthermore, short-channel characteristics for the n-channel and p-channel SELBOX JL FinFET have been discussed. For channel length of 5 nm (which is a future technology node for mass production of semiconductor devices and systems), SELBOX device has shown favourable value of I_ON/I_OFF ratio as 10⁶ and SS as 96.86 mV/Dec. SELBOX JL FinFET has shown more immunity towards self-heating effect compared to the SOI JL FinFET. Performance of the SELBOX JL FinFET can be enhanced further independently by tuning various parameters such as the buried oxide thickness, the gap between buried oxide layers, substrate doping, and substrate bias.