Study of parametric variations on hetero-junction vertical t-shape TFET for suppressing ambipolar conduction

Abstract

This paper investigates a hetero-junction vertical t-shape tunnel field effect transistor and discussed various methods for the suppression of ambipolar conduction for the first-time utilizing computer aided design sentaurus simulation tool. This device is primarily consisting of dual gate silicon based gated p-i-n diode for eminent control over the channel. Further, introduction to the 10 nm silicon germanium layer to the channel makes aggressive improvement to the device characteristics. Unlike to the conventional TFET, we have considered the effective techniques like gate-on-drain overlapping, gate-on-channel underlapping and different drain doping concentration up to 1 × 10¹⁸ cm⁻³, which are used to conquer the ambipolar conduction by increasing the tunneling barrier width at the drain channel edges. The device surface potential performance is also analyzed for different parameters like drain doping concentration, gate-source voltage, silicon germanium Si_1-xGe_x mole fraction x and gate oxide thickness. Moreover, the vertical and lateral electric field inspect for determining the tunneling rate. The path distribution of source channel and drain in vertical direction will increase the scalability of the simulated device.